The present invention relates generally to semiconductor integrated logic circuits and, more particularly, to a BIFET logic circuit with fast switching and low power dissipation.
Advances in semiconductor processing technology have provided the ability to fabricate large numbers of active devices on a single chip. Bipolar transistors are the preferred active devices for such chips because of their fast switching speeds, reduced delay per unit load, and ability to drive large capacitive loads due to their high current gain. In particular, during transient periods the bipolar current gain allows the fast charging and discharging of capacitive loads, resulting in high switching speeds and decreased fanout delays.
However, the limiting factor preventing the design of a bipolar chip with more than 20,000 circuits is power dissipation. The few low power (less than 200 microwatt) bipolar circuits available are slow and difficult to implement due to high resistance values.
In order to obviate the power dissipation problem, logic functions are now being designed to use CFET (complementary field effect transistor) circuits, with their attendant low power consumption, in combination with a bipolar push-pull driver output circuit. This combination, referred to as a BIFET or BICMOS circuit, utilizes the high noise immunity, high input impedance, and low power consumption characteristics of the FET to perform the actual logic function, while obviating the FET's low transconductance and poor ability to drive heavy capacitive loads by using a bipolar driver output circuit.
A typical CFET logic circuit utilizes one or more P type FETs connected in one of either a series or a parallel connection, which, in turn, is connected in series to one or more N type FETs connected in the other of either a series or a parallel connection. Each input line is connected to the gate of a different P type FET and to the gate of a different N type FET. Output lines from this CFET logic circuit are connected to drive base currents for a first bipolar transistor connected to source current on an output line, and a second bipolar transistor connected to sink current from the output line.
In most prior art circuits of this type, the N FETs are connected between the output line and the second transistor base. This connection, in combination with the NFET connection to the power supply through the PFETs, provides the base current to the second bipolar transistor to thereby sink current from the output line when these N FETs are conducting. For example, see U.S. Pat. No. 4,616,146.
However, it has been discovered that during a switching of the output line from a high voltage, for example 3 volts, to a low voltage close to ground, the above-recited circuit connection causes an initial fast voltage drop on the output line to approximately 0.7 volts, followed by a very slow drop from 0.7 volts to approximately ground. This slow voltage drop period is due to the fact that the base current for the current sinking second bipolar transistor, after the P FETs stop conducting, is actually coming from the output line itself, which line has already sunk a large portion of its capacitive charge during the initial fast voltage drop. In essence, when the output voltage drops to approximately 0.7 volts, the base of the current sinking second transistor also drops to 0.7 volts (since the NFETs connected from the base to the output line are on and the NFET source cannot have a higher voltage than its drain). Therefore, this second transistor turns off (a V.sub.BE below 0.7 volts is not sufficient to maintain the transistor in conduction) causing the collector current to go to zero. Thus, the second transistor. Also, as the output line drops no longer provides a sink for the capacitive current of the output line, and the output voltage cannot continue to drop quickly below 0.7 volts. Thus, the circuit must rely on leakage currents through the second bipolar transistor to sink the remainder of the capacitive charge on the output line to thereby drop the output line to approximately ground potential.
This slow output line voltage drop from 0.7 volts to ground makes this circuit output line unsuitable for driving low-threshold CFET circuits because, during a portion of this slow voltage drop, both the P and N type FETs are conductive in the following CFET circuit, causing a low impedance connection between Vcc & ground. In this regard, the voltage range above the 0.4 volts V.sub.GS threshold for a typical N type FET, and below the 0.6 volt V.sub.SG threshold for a typical P type FET, causes both types of devices to be conductive. Accordingly, the slow voltage drop through this 0.4-0.6 voltage range causes a substantial power dissipation in any CFET circuit being driven by the output line.
Additionally, most prior art BIFET circuits of the type described require two bipolar transistors, plus at least three times the circuit fan-in of FETs, plus an additional FET, in order to implement their logic. However, as the circuit fan-in becomes large, the active device count for such a circuit becomes prohibitive.
The invention as claimed is intended to remedy the above-described problems.
The advantage offered by the present invention is a high speed switching of the output line down to a reference potential which may be close ground potential. Accordingly, the circuit of the present invention can be used to directly drive low-threshold CFET circuits. Additionally, the circuit of the present invention utilizes an active device count of two times the circuit fan-in plus two FETs, plus the two bipolar transistors. This reduced active device count is a significant advantage as the circuit fan-in increases.